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packetConstants.h
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1 #ifndef __PACKETCONSTANTS_H__
2 #define __PACKETCONSTANTS_H__
3 
4 
5 /* Misc. values */
6 #define MAX_OUTLENGTH 100000
7 
8 // define some offset which takes us out well > 30,000 for our ID;s
9 #define IDOFFSET 30000
10 
11 // normal pass through mode
12 #define IDDCM0OFFSET 400
13 // normal fpga zero suppression mode
14 #define IDDCM1OFFSET 500
15 // extra
16 #define IDDCM2OFFSET 600
17 // level1 packets
18 #define IDLL1OFFSET 700
19 #define IDL2OFFSET 750
20 
21 // alternate (long) format pass through mode
22 #define IDDCM3OFFSET 800
23 // short format (emcal, etc)
24 #define IDDCMSOFFSET 900
25 
26 // ---------------------------------------------------------------------
27 // IDCRAW requests the subevent to be copied without any decoding
28 #define IDCRAW IDOFFSET + 0
29 
30 // ---------------------------------------------------------------------
31 // IDDGEN uses the standard decoding method imbedded in the subevent
32 // header in the new data format
33 #define IDDGEN IDOFFSET + 1
34 
35 // ---------------------------------------------------------------------
36 // IDHCPY requests only the subevent header (or the Event header) to be
37 // copied:
38 #define IDHCPY IDOFFSET + 2
39 
40 // ---------------------------------------------------------------------
41 // the next methods < 10 use what we consider standard methods by
42 // now, i.e., no scheme proprietary to one particular hardware brand
43 
44 #define ID1STR IDOFFSET + 3
45 #define IDCSTR IDOFFSET + 4
46 #define ID2EVT IDOFFSET + 5
47 #define ID4EVT IDOFFSET + 6
48 #define ID2SUP IDOFFSET + 7
49 #define ID4SCALER IDOFFSET + 8
50 #define IDRTCLOCK IDOFFSET + 9
51 
52 // ---------------------------------------------------------------------
53 // the next methods are for the hammond/g-2 board.
54 
55 #define IDHAMMONDSET IDOFFSET + 31
56 #define IDHAMMOND IDOFFSET + 32
57 
58 #define IDSAM IDOFFSET + 40
59 
60 #define IDMIZNHC IDOFFSET + 41
61 
62 #define IDDCFEM IDOFFSET + 51
63 
64 
65 // the "level 0", meaning the raw untreated FEM data
66 
67 #define IDBBC_DCM0 IDDCM0OFFSET + 1
68 #define IDMVD_DCM0 IDDCM0OFFSET + 2
69 #define IDDCH_DCM0 IDDCM0OFFSET + 3
70 #define IDPC_DCM0 IDDCM0OFFSET + 4
71 #define IDTEC_DCM0 IDDCM0OFFSET + 5
72 #define IDRICH_DCM0 IDDCM0OFFSET + 6
73 #define IDTOF_DCM0 IDDCM0OFFSET + 7
74 #define IDPBSC_DCM0 IDDCM0OFFSET + 8
75 #define IDPBGL_DCM0 IDDCM0OFFSET + 9
76 #define IDMUTA_DCM0 IDDCM0OFFSET + 10
77 #define IDMUTC_DCM0 IDDCM0OFFSET + 11
78 #define IDMUID_DCM0 IDDCM0OFFSET + 12
79 #define IDZDC_DCM0 IDDCM0OFFSET + 13
80 #define IDPXL_DCM0 IDDCM0OFFSET + 24
81 
82 // the "level 1", FEM data zero-suppressed by the FPGA
83 
84 #define IDBBC_DCM1 IDDCM1OFFSET + 1
85 #define IDMVD_DCM1 IDDCM1OFFSET + 2
86 #define IDDCH_DCM1 IDDCM1OFFSET + 3
87 #define IDPC_DCM1 IDDCM1OFFSET + 4
88 #define IDTEC_DCM1 IDDCM1OFFSET + 5
89 #define IDRICH_DCM1 IDDCM1OFFSET + 6
90 #define IDTOF_DCM1 IDDCM1OFFSET + 7
91 #define IDPBSC_DCM1 IDDCM1OFFSET + 8
92 #define IDPBGL_DCM1 IDDCM1OFFSET + 9
93 #define IDMUTA_DCM1 IDDCM1OFFSET + 10
94 #define IDMUTC_DCM1 IDDCM1OFFSET + 11
95 #define IDMUID_DCM1 IDDCM1OFFSET + 12
96 #define IDZDC_DCM1 IDDCM1OFFSET + 13
97 
98 // the "level 2", data further compressed by the DSP
99 
100 #define IDBBC_DCM2 IDDCM2OFFSET + 1
101 #define IDMVD_DCM2 IDDCM2OFFSET + 2
102 #define IDDCH_DCM2 IDDCM2OFFSET + 3
103 #define IDPC_DCM2 IDDCM2OFFSET + 4
104 #define IDTEC_DCM2 IDDCM2OFFSET + 5
105 #define IDRICH_DCM2 IDDCM2OFFSET + 6
106 //#define IDTOF_Q1Q2T3T4 IDDCM2OFFSET + 7
107 #define IDTOF_DCM2 IDDCM2OFFSET + 7
108 #define IDEMC_OLDSTYLE IDDCM2OFFSET + 58
109 #define IDPBGL_DCM2 IDDCM2OFFSET + 9
110 #define IDMUTA_DCM2 IDDCM2OFFSET + 10
111 #define IDMUTC_DCM2 IDDCM2OFFSET + 11
112 //#define IDMUID_DCM2 IDDCM2OFFSET + 12
113 #define IDZDC_DCM2 IDDCM2OFFSET + 13
114 
115 // the "level 3", alternate (long) format in pass through mode
116 
117 #define IDBBC_DCM3 IDDCM3OFFSET + 1
118 #define IDMVD_DCM3 IDDCM3OFFSET + 2
119 #define IDDCH_DCM3 IDDCM3OFFSET + 3
120 // moved to idpc_fpga #define IDPC_DCM3 IDDCM3OFFSET + 4
121 #define IDTEC_DCM3 IDDCM3OFFSET + 5
122 #define IDRICH_DCM3 IDDCM3OFFSET + 6
123 #define IDTOF_DCM3 IDDCM3OFFSET + 7
124 // emc FEM to DCM long format (192 channels, user words, ...)
125 #define IDPBSC_DCM3 IDDCM3OFFSET + 8
126 #define IDPBGL_DCM3 IDDCM3OFFSET + 9
127 
128 #define IDFVTX_DCM0 IDDCM0OFFSET + 25
129 #define IDFVTX_SIM IDDCM0OFFSET + 48
130 
131 
132 // the emc short formats
133 
134 #define IDPBSC_DCMS 908
135 #define IDPBGL_DCMS 909
136 
137 // the emc zero-suppressed short formats (3 words per channel+address)
138 
139 #define IDPBSC_DCMZS 608
140 #define IDPBGL_DCMZS 609
141 
142 
143 // the "pbsc 32 channel format"
144 
145 #define IDEMC_DCM32 808
146 #define IDPBGL_DCM32 809
147 
148 // the emc non-suppressed format from the DCM (144 channels, no user words,...)
149 #define IDPBSC_DCM5 1008
150 #define IDPBGL_DCM5 1009
151 
152 // the emc zero-suppressed format from the DCM (5 words per channel+address)
153 #define IDPBSC_DCM05 1108
154 #define IDPBGL_DCM05 1109
155 
156 // the fcal zero-suppressed formats (it will use the emcs 1008 1108 packets)
157 #define IDFCAL_FPGA 1016
158 #define IDFCAL_FPGA0SUP 1216
159 #define IDFCAL_FPGA3 1316
160 #define IDFCAL_FPGA0SUP3 1116
161 
162 
163 #define IDTOF_DCM16 307
164 
165 // IDDCM3OFFSET = 800
166 #define IDMUTA_DCM3 IDDCM3OFFSET + 10
167 #define IDMUTC_DCM3 IDDCM3OFFSET + 11
168 #define IDMUID_DCM3 IDDCM3OFFSET + 12
169 #define IDZDC_DCM3 IDDCM3OFFSET + 13
170 
171 #define IDFOCAL_FPGATEST 725
172 
173 #define IDMUTRG_DCM0 791
174 
175 
176 // we start two new series -- 1000 : through fpga but not zero-supressed
177 // -- 1100 : through fpga AND zero-supressed
178 
179 
180 
181 
182 #define IDBBC_FPGA 1001
183 #define IDBBC_FPGA0SUP 1101
184 
185 #define IDMVD_FPGA 1002
186 #define IDMVD_FPGA0SUP 1102
187 
188 #define IDMVD_PED_FPGA0SUP 1502
189 
190 #define IDPC_FPGA 804
191 #define IDPC_FPGA0SUP 1104
192 
193 #define IDRICH_FPGA 1006
194 #define IDRICH_FPGA0SUP 1106
195 
196 #define IDTOF_FPGA 1007
197 #define IDTOF_FPGA0SUP 1107
198 
199 #define IDTOFW_FPGA 1057
200 #define IDTOFW_FPGA0SUP 1157
201 
202 #define IDEMC_FPGA 1008
203 #define IDEMC_FPGA0SUP 1108
204 
205 #define IDEMC_FPGASHORT 1208
206 #define IDEMC_FPGASHORT0SUP 1308
207 
208 #define IDEMC_FPGA3WORDS 1408
209 #define IDEMC_FPGA3WORDS0SUP 1508
210 
211 #define IDEMC_REFERENCE 1058
212 #define IDEMC_REFERENCE0SUP 1158
213 
214 #define IDEMC_SHORTREFERENCE 1068
215 #define IDEMC_SHORTREFERENCE0SUP 1168
216 
217 #define IDMUTC_FPGA 1011
218 #define IDMUTC_FPGA0SUP 1111
219 #define IDMUTC_FPGASHORT 1211
220 #define IDMUTC_FPGASHORTSUP 1311
221 #define IDMUTC_FPGANEW 1411
222 #define IDMUTC_FPGANEWSUP 1511
223 
224 #define IDMUTC_15_FPGA 1051
225 #define IDMUTC_15_FPGA0SUP 1151
226 
227 #define IDMUID_FPGA 1012
228 #define IDMUID_FPGA0SUP 1112
229 
230 #define IDZDC_FPGA 1013
231 #define IDZDC_FPGA0SUP 1113
232 
233 #define IDNTCT0_FPGA 1015
234 #define IDNTCT0_FPGA0SUP 1115
235 
236 #define IDRPC_DCM0 1019
237 #define IDRPC_FPGA 1219
238 #define IDRPC_FPGA0SUP 1319
239 
240 
241 // HBD gets number 22
242 #define IDHBD_FPGA 1022
243 #define IDHBD_FPGA0SUP 1122
244 #define IDHBD_FPGASHORT 1222
245 #define IDHBD_FPGASHORT0SUP 1322
246 #define IDHBD_FPGA3SAMPLES 1422
247 #define IDHBD_FPGA3SAMPLES0SUP 1522
248 
249 // RXNP gets 23
250 
251 #define IDRXNP_FPGASHORT 1323
252 #define IDRXNP_FPGASHORT0SUP 1423
253 
254 // the "LL1", level 1 trigger info
255 
256 #define IDBBC_LL1 IDLL1OFFSET + 1
257 #define IDMVD_LL1 IDLL1OFFSET + 2
258 #define IDRICH_LL1 IDLL1OFFSET + 6
259 #define IDTOF_LL1 IDLL1OFFSET + 7
260 #define IDPBSC_LL1 IDLL1OFFSET + 8
261 #define IDPBGL_LL1 IDLL1OFFSET + 9
262 #define IDMUIDH_LL1 IDLL1OFFSET + 12
263 #define IDMUIDV_LL1 IDLL1OFFSET + 13
264 #define IDGL1 IDLL1OFFSET + 14
265 #define IDGL1P IDDCM3OFFSET + 14
266 #define IDGL1PSUM 914
267 #define IDGL1PSUMOBS 818
268 #define IDEMCRICH_LL1 IDLL1OFFSET + 15
269 #define IDNTCZDC_LL1 IDLL1OFFSET + 16
270 #define IDGL1_EVCLOCK IDLL1OFFSET + 17
271 #define IDERT_E_LL1 IDLL1OFFSET + 18
272 #define IDERT_W_LL1 IDLL1OFFSET + 19
273 #define IDBIG_LL1 IDLL1OFFSET + 77
274 
275 // L2 packets
276 //
277 #define IDL2DECISION IDL2OFFSET
278 #define IDL2PRIMITIVE IDL2OFFSET + 1
279 
280 
281 // the CDEV data formats, starting from 2000
282 
283 #define IDCDEVIR 2001
284 #define IDCDEVDVM 2002
285 #define IDCDEVRING 2003
286 #define IDCDEVWCMHISTORY 2004
287 #define IDCDEVSIS 2005
288 #define IDCDEVPOLARIMETER 2006
289 #define IDCDEVPOLDATA 2007
290 #define IDCDEVPOLARIMETERTARGET 2008
291 #define IDCDEVBPM 2009
292 #define IDCDEVMADCH 2010
293 #define IDGL1PSCALER 2011
294 #define IDCDEVRINGPOL 2012
295 #define IDCDEVRINGFILL 2013
296 #define IDCDEVBUCKETS 2014
297 #define IDCDEVRINGNOPOL 2015
298 #define IDCDEVPOLARIMETERZ 2016
299 #define IDCDEVDESCR 2017
300 #define IDSTARSCALER 2098
301 
302 #define IDDIGITIZER_31S 93
303 #define IDDIGITIZER_12S 94
304 #define IDDIGITIZER_16S 95
305 
306 #define IDDIGITIZERV3_2S 162
307 #define IDDIGITIZERV3_4S 164
308 #define IDDIGITIZERV3_6S 166
309 #define IDDIGITIZERV3_8S 168
310 #define IDDIGITIZERV3_10S 170
311 #define IDDIGITIZERV3_12S 172
312 #define IDDIGITIZERV3_14S 174
313 #define IDDIGITIZERV3_16S 176
314 #define IDDIGITIZERV3_18S 178
315 #define IDDIGITIZERV3_20S 180
316 #define IDDIGITIZERV3_22S 182
317 #define IDDIGITIZERV3_24S 184
318 #define IDDIGITIZERV3_26S 186
319 #define IDDIGITIZERV3_28S 188
320 #define IDDIGITIZERV3_30S 190
321 
322 #define IDLL1_20S 141
323 #define IDLL1v2_20S 142
324 
325 
326 #define IDDIGITIZER_CTRL 2099
327 
328 // LL1
329 
330 #define IDLL1_20S 141
331 #define IDLL1v2_20S 142
332 
333 // EMC data header and trailer length
334 
335 #define EMC_SUPPRESSED_DATA_HEADER_LENGTH 8
336 #define EMC_DATA_TRAILER_LENGTH 10
337 #define EMC_SHORT_DATA_HEADER_LENGTH 9
338 #define EMC_LONG_DATA_HEADER_LENGTH 9
339 #define EMC_WORDS_PER_CH_SHORT 3
340 #define EMC_WORDS_PER_CH_LONG 5
341 #define EMC_DCMDATA_HEADER_LENGTH 8
342 #define EMC_DCMDATA_TRAILER_LENGTH 2
343 #endif /* __PACKETCONSTANTS_H__ */
344 
345 
346